The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device which can prevent or inhibit the deterioration of transistor characteristics formed in a peripheral region and a method for manufacturing the same.
In general, memory devices are generally divided into volatile RAMs (random access memory) that loses inputted information when power is interrupted and non-volatile ROMs (read-only memory) that maintain the stored state of inputted information even when power is interrupted. As to volatile RAMs, a DRAM (dynamic RAM) and an SRAM (static RAM) can be mentioned. As to non-volatile ROMs, a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
While the DRAM belongs to an excellent memory device, the DRAM must have high charge storing capacity. To this end, since the surface area of an electrode must be increased, it is difficult to accomplish a high level of integration with DRAMs. Further, in the flash memory devices, due to the fact that two gates are stacked on each other, a high operation voltage is required as compared to a power supply voltage. According for flash memory devices, a separate booster circuit is needed to generate a voltage needed for write and delete operations. Therefore for flash memory devices it is also difficult to achieve a high level of integration.
Under these situations, much research has been undertaken with the hopes of developing alternate novel memory devices that still retain simple configurations and are able to achieve a high level of integration while retaining the desirable characteristics of non-volatile memory devices. As one example, a phase change memory device has been disclosed in the art. The operational basis of phase change memory device is that a phase change layer is interposed between a bottom electrode and a top electrode. The phase change layer can be in a crystalline state to an amorphous state which can be brought about by imposing a current flow between the bottom electrode and the top electrode. Accordingly, the information can be stored in a phase change memory cell by exploiting the physical phenomenon of the difference in resistance between the crystalline state and the amorphous state.
One of the most important factors that must be considered to develop a phase change memory device is to reduce or minimize programming current. Accordingly, recent phase change memory devices adopt vertical PN diodes, having high current flow rate, as cell switching elements in place of NMOS transistors. When the vertical PN diodes are adopted, because the vertical PN diodes have increased current flow rate and the size of cells can be decreased, it is possible to realize a highly integrated phase change memory device.
While not shown in a drawing, phase change memory devices can employ the vertical PN diodes, as cell switching elements. The vertical PN diodes are formed in a cell region after forming gates in a peripheral region. Due to this fact, the vertical PN diodes cannot but be formed higher than the gates. Accordingly, defects are likely to be caused in the transistors which are formed in the peripheral region.
In order to form the vertical PN diodes, in the conventional art, after defining holes in an insulation layer, an epi-silicon layer is formed in the holes through a selective epitaxial growth (SEG) process. Then, N-type and P-type impurities are ion-implanted into the epi-silicon layer. In this regard, since the epi-silicon layer is formed higher than the gates formed in the peripheral region, when conducting the SEG process as a high temperature process, impurities ion-implanted into the source and drain areas of the transistors in the peripheral region diffuse. As a result, a problem is caused in that the characteristics of the transistors in the peripheral region deteriorate.
Meanwhile, in order to reduce the programming current of a phase change memory device, it is necessary to decrease the contact interface between each heater and a phase change layer. This can be accomplished by decreasing the size of the heater. However, since the size distribution of the holes in which heaters are to be formed cannot but be wide due to the limitations in a lithography process, programming current distribution also becomes wide. As a consequence, it is difficult to secure the characteristics of the phase change memory device.
In phase change memory devices, current flow from the cell switching elements is transmitted to the phase change layer through the heaters. If the size of the heaters is decreased so as to reduce the programming current of the phase change memory device, when reset programming is performed, that is, when the phase change layer is quenched after being melted, heat transfer to the heaters does not quickly occur. As a result nucleation is caused in the phase change layer, and reset resistances cannot be produced at a high level. As a result, the difference between reset resistance and set resistance is not substantial enough for an adequate sensing margin to be exploited in which durability characteristics are likely to degrade.